\section{Experimental evaluation}\label{exp}
In this section, we provide comprehensive evaluations to demonstrate the efficiency of our proposed backup flow. We first give the experiment setup description. Then we evaluate the efficiency of our proposed partial backup scheme, pre-writeback policy, the capacitor requirement and the overall inrush current.

\subsection{Experiment Setup}
We implement our nvSRAM-based L1 cache design in a popular computer architecture simulator gem5~\cite{binkert2011gem5}. We configured it to model an ARM Cortex-A8 processor, which has been implemented in several SoCs including Allwinner A1X, Samsung Exynos 3110, etc. To model a fully nonvolatile memory system, we assume that the L1 cache is nvSRAM based and the L2 cache is configured as asymmetric-access STT-RAM based cache. The whole parameters are listed in Table~\ref{tab1}.

\input{tab_setup}

All benchmarks come from Mibench~\cite{Mibench}. For each benchmark, we sample 50 operation points uniformly and record the prediction results to compare with the ideal results. The power input profile is derived from a vibration-based energy harvester. 